High-Level Design Group


Group Leader Professor Kunle Olukotun


Students Jeremy Levitt

Victor Lam

Rachid Helaihel

Mike Chen



Research Processor verification

High-level area and timing estimation

Hardware-software co-synthesis of Java specifications



Stanford Links... Stanford CAD group

Computer Systems Lab

Electrical Engineering Dept

Computer Science Dept



Comments or questions to be addressed to Rachid Helaihel. (last update -- 10/17/97)


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