High-Level Design Group



	Professor Kunle Olukotun

	Jeremy Levitt Victor Lam Rachid Helaihel Mike Chen

	Processor verification High-level area and timing estimation Hardware-software co-synthesis of Java specifications

	Stanford CAD group Computer Systems Lab Electrical Engineering Dept Computer Science Dept

Comments or questions to be addressed to Rachid Helaihel. (last update -- 10/17/97)